Senior Silicon Engineering - Surface
Herzliya, Tel Aviv, Israel | Hardware Engineering | Mar 10, 2022


Work with system/architecture team to understand the top level requirements of the digital functions and develop detailed specifications

Implement the function in high-quality Verilog RTL to specification.

Support the DV team to insure bug-free first silicon.

Perform all design integration activities like Lint, CDC, Synthesis

Work with physical design team on STA, power and ECO

Support silicon bring-up, performance and power characterization.

 



Responsibilities

  • 10+ experience in logic design including Verilog RTL design
  • Knowledge of best practices with respect to implementation of digital logic
  • Experience  in Low Power techniques and Multiple Clock domain crossing
  • Understanding of logic synthesis,  timing constraints , timing closure, STA, Equivalence checking, gate level simulation
  • Understanding of  ASIC DFT, such as scan, mbist and test pattern generation
  • Knowledge in Python, TCL, shell scripts is desired
  • Understanding of  design verification and ability to write self-checking tests
  • Experience in FPGA prototype flow


Qualifications

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. 

 

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.




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